1. Field of the Invention
The present invention relates to pipelined loop structures that are produced by reconfigurable hardware compilers. More specifically, the invention relates to compiling pipelined loop structures that have a variable number of loop cycles and variable length clock latency.
2. Relevant Background
As instruction processors continue to increase rapidly in processing power, they are used more often to do computationally intensive calculations that were once exclusively done by supercomputers. However, there are still computationally intensive tasks, including, for example, compute-intensive image processing and hydrodynamic simulations that remain impractical to do on modem instruction processors.
Reconfigurable computing is a technology receiving increased interest in the computing arts. Traditional general purpose computing is characterized by computer code executed serially on one or more general purpose processors. Reconfigurable computing is characterized by programming reconfigurable hardware, such as Field Programmable Gate Arrays (FPGAs) to execute logic routines.
Reconfigurable computing offers significant performance advances in computation-intensive processing. For example, the reconfigurable hardware may be programmed with a logic configuration that has more parallelism and pipelining characteristics than a conventional instruction processor. Also, the reconfigurable hardware may be programmed with a custom logic configuration that is very efficient for executing the tasks assigned by the program. Furthermore, dividing a program's processing requirements between the instruction processor and the reconfigurable hardware may increase the overall processing power of the computer.
Software programs that are written in a high level language like, for example, C or Fortran can be converted into software that is executable in reconfigurable hardware with Multi-Adaptive Processor (“MAP”) compilers. Loop structures in the high level language may be converted by the MAP compiler into a form that exploits parallelism and pipelining characteristics of reconfigurable hardware.
Unfortunately, existing MAP compilers only work with a small subset of all loop structures where the loops have a predetermined number of loop iterations before the loop terminates and that have periods of one clock, among other requirements. Thus, there remains a need for compilers that can compile loop structures where the loop does not terminate after a predetermined number of iterations and where the loop has a period greater than one clock.